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| INTEGRATED CIRCUITS DATA SHEET SAA8115HL Digital camera USB interface Preliminary specification Supersedes data of 1999 Jun 28 File under Integrated Circuits, IC22 2000 Jan 27 Philips Semiconductors Preliminary specification Digital camera USB interface CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 9 9.1 9.2 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Video synchronization Frame rate converter and SDRAM interface Video formatter: downsampler and cutter Compression engine Transfer buffer USB video FIFO PSIE-MMU, I2C-bus interface and USB RAM space ATX interface Audio Sensor pulse pattern generator Power management Power supply CONTROL REGISTER DESCRIPTION SNERT (UART) I2C-bus interface 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 LIMITING VALUES SAA8115HL THERMAL CHARACTERISTICS OPERATING CHARACTERISTICS TIMING APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 2000 Jan 27 2 Philips Semiconductors Preliminary specification Digital camera USB interface 1 FEATURES SAA8115HL * VGA (progressive mode), CIF and medium resolution (PAL non-interlaced mode) CCD sensors compliant * D1 digital video input (8 bits YUV 4 : 2 : 2 time multiplexed) * Internal Pulse Pattern Generator (PPG) dedicated for VGA Panasonic, CIF and medium resolution Sharp sensors or compatibles, and frame rate selection * Frame rate converter * SDRAM interface for high quality VGA snapshot (uncompressed 4 : 2 : 2 or 4 : 2 : 0) * Downsampler and scaler (programmable formatter for CIF, QCIF, sub-QCIF, SIF and QSIF) controlled via SNERT (UART) interface * Flexible compression engine controlled via SNERT (UART) interface * Selectable output frame rate (up to 15 fps in VGA, up to 30 fps in CIF and QCIF) * Video packetizer FIFO * I2C-bus interface for communication between the USB protocol hardware and the external microcontroller * Microphone/audio input to USB (microphone supply, controllable gain and ADC) * Integrated analog bus driver (ATX) * Integrated main oscillator * Integrated 5 V power supply and reset circuit including functionalities for bus-powered USB device * Programmable (frequency and duty cycle) switch mode power signal for CCD supply * Miscellaneous functions (e.g. power management, PLL for audio frequencies). 2 APPLICATIONS Low-cost desktop video applications with USB interface. 3 GENERAL DESCRIPTION The SAA8115HL is the second generation of integrated circuit applicable in PC video cameras to convert D1 video signals and analog audio signals to properly formatted USB packets. This powerful successor of the SAA8117HL can handle up to 15 fps in VGA format or 30 fps in CIF format. High snapshot quality is achievable using the SDRAM interface to an external memory. It is designed as a back-end of the SAA8112HL (general camera digital processing IC) and is optimized for use with the TDA8784 to TDA8787 (camera pre-processing ICs). 2000 Jan 27 3 Philips Semiconductors Preliminary specification Digital camera USB interface 4 ORDERING INFORMATION TYPE NUMBER SAA8115HL PACKAGE NAME LQFP144 DESCRIPTION SAA8115HL VERSION SOT486-1 plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm 5 QUICK REFERENCE DATA Measured over full voltage and temperature range SYMBOL VDDD VDDA VDDA_USB IDD(tot) VI VO fclk Ptot Tstg Tamb Tj Note 1. This concerns pins VBUS1 and VBUS2. PARAMETER digital supply voltage analog supply voltage analog supply voltage from USB total supply current input signal levels output signal levels clock frequency total power dissipation storage temperature ambient temperature junction temperature Tamb = 70 C Tamb = 25 C note 1 VDDD = 3.3 V 3.0 V < VDDD < 3.6 V 3.0 V < VDDD < 3.6 V CONDITIONS MIN. 3.0 3.0 4.0 - TYP. 3.3 3.3 5.0 - MAX. 3.6 3.6 5.5 tbf V V V mA V V MHz mW C C C UNIT low voltage TTL compatible low voltage TTL compatible - - -55 0 -40 48 - - 25 - - tbf - 70 +125 2000 Jan 27 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth DGND1 to DGND4 AGND1 to AGND6 SUSPREADYNOT VDDD1 to VDDD3 VDDA1 to VDDA6 RESERVED1 to RESERVED6 GND1 to GND7 VDD1 to VDD6 REF1 to REF3 SNAPSHOT CLOCKON SUSPEND GENPOR M3 to M0 SDCLK CLKEN RESET RASB CASB DQM WEB AD10 to AD0 DQ15 to DQ0 YUV7 to YUV0 LLC HREF VS 48, 47, 45, 44, 42, 39, 38, 40, 41, 43, 46 24, 53, 102 52 56 57 58 55 59 51 7, 16, 82, 84, 37, 50, 85, 122, 69, 141 124, 125 23, 29, 33 115, 116, 79, 88, 6, 18, 54, 101 117, 118 93, 119, 49, 68, 123, 134 78, 98, 142 126, 127, 128 83, 86, 89, 96, 97, 129 103 100 109 112 110 111 108 SMP CSB TRC VBUS1 LXDOWN XOUT B1 to B4 VBUS2 SWITCHED5V MICSUPPLY SHUTTER A1 to A4 C1 to C4 FCDS MICIN HD LXUP RG CLK1 CLK2 POR DCP BCP VD FS 3V3 OFF XIN 2000 Jan 27 77, 76, 75, 74, 67, 65, 62, 60, 61, 63, 64, 66, 70, 71, 72, 73 28, 27, 26, 25 22, 21, 20, 19 30 31 32 FRAME RATE CONVERTER VIDEO FORMATTER SDRAM INTERFACE 6 Philips Semiconductors Digital camera USB interface BLOCK DIAGRAM USB RAM SPACE POWER MANAGEMENT 99 104 105 UCINT UCPOR UCCLK COMPRESSION ENGINE TRANSFER BUFFER USB VIDEO FIFO PSIE MMU ATX 80 81 ATXDP ATXDM 5 AUDIO PLL SNDA SNCL SNRES 34 35 36 AUDIO ADC AUDIO VARIABLE GAIN AMPLIFIER AUDIO LOW NOISE AMPLIFIER I2C-BUS INTERFACE 106 107 SCL SDA SAA8115HL SNERT INTERFACE 130 VGAIN PULSE PATTERN GENERATOR (PPG) DC-TO-DC CONVERTER MAIN OSCILLATOR MICROPHONE SUPPLY 131 LNAOUT 139, 140, 137, 138, 3, 2, 143, 144 136, 135 1, 4 8 5 9 10 12 13 14 15 11 17 87 90 91 92 94 95 113 114 120 121 133 132 FCE349 Preliminary specification SAA8115HL Fig.1 Block diagram. Philips Semiconductors Preliminary specification Digital camera USB interface 7 PINNING SYMBOL C3 C2 C1 C4 SHUTTER GND1 VDD1 RG FS FCDS CLK1 DCP BCP VD HD VDD2 CLK2 GND2 YUV0 YUV1 YUV2 YUV3 DGND1 VDDD1 YUV4 YUV5 YUV6 YUV7 DGND2 LLC HREF VS RESET SNDA SNCL SNRES PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TYPE(1) O O O O O P P O O O O O O O O P O P I I I I P P I I I I P I I I I I/O I I DESCRIPTION horizontal CCD transfer pulse output horizontal CCD transfer pulse output (FH1) horizontal CCD transfer pulse output (FH2) horizontal CCD transfer pulse output shutter control output for CCD charge reset ground 1 for output buffers supply voltage 1 for output buffers reset output for CCD output amplifier gate data sample-and-hold pulse output to TDA8784/87 (SHD) preset sample-and-hold pulse output to TDA8784/87 (SHP) pixel clock to TDA8784/87 and SAA8112HL dummy clamp pulse output to TDA8784/87 optical black clamp pulse output to TDA8784/87 vertical definition pulse to SAA8112HL horizontal definition pulse to SAA8112HL supply voltage 2 for output buffers double pixel clock to SAA8112HL ground 2 for output buffers multiplexed YUV bit 0 multiplexed YUV bit 1 multiplexed YUV bit 2 multiplexed YUV bit 3 SAA8115HL digital ground 1 for input buffers, predrivers and for the digital core digital supply voltage 1 for input buffers, predrivers and one part of the digital core multiplexed YUV bit 4 multiplexed YUV bit 5 multiplexed YUV bit 6 multiplexed YUV bit 7 digital ground 2 for input buffers, predrivers and for the digital core line-locked clock input (delayed CLK2) for YUV-port from SAA8112HL horizontal reference input for YUV-port from SAA8112HL vertical synchronization input for YUV-port from SAA8112HL Power-on reset input (for video processing and PPG) data input/output for SNERT-interface (communication between SAA8115HL and SAA8112HL) clock input for SNERT-interface (communication between SAA8115HL and SAA8112HL) reset input for SNERT-interface (communication between SAA8115HL and SAA8112HL) 2000 Jan 27 6 Philips Semiconductors Preliminary specification Digital camera USB interface SAA8115HL SYMBOL VDD3 AD4 AD5 AD3 AD2 AD6 AD1 AD7 AD8 AD0 AD9 AD10 GND3 VDD4 CSB RASB VDDD2 DGND3 CLKEN CASB WEB SDCLK DQM DQ8 DQ7 DQ9 DQ6 DQ5 DQ10 DQ4 DQ11 GND4 VDD5 DQ3 DQ2 DQ1 DQ0 DQ12 DQ13 DQ14 DQ15 2000 Jan 27 PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 TYPE(1) P O O O O O O O O O O O P P O O P P O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P I/O I/O I/O I/O I/O I/O I/O I/O SDRAM output address bit 4 SDRAM output address bit 5 SDRAM output address bit 3 SDRAM output address bit 2 SDRAM output address bit 6 SDRAM output address bit 1 SDRAM output address bit 7 SDRAM output address bit 8 SDRAM output address bit 0 SDRAM output address bit 9 SDRAM output address bit 10 ground 3 for output buffers DESCRIPTION supply voltage 3 for output buffers supply voltage 4 for output buffers SDRAM chip select output SDRAM row address strobe output digital supply voltage 2 for the switchable digital core digital ground 3 for input buffers, predrivers and for the digital core SDRAM clock enable output SDRAM column address strobe output SDRAM write enable output SDRAM clock output SDRAM data mask enable SDRAM data I/O bit 8 SDRAM data I/O bit 7 SDRAM data I/O bit 9 SDRAM data I/O bit 6 SDRAM data I/O bit 5 SDRAM data I/O bit 10 SDRAM data I/O bit 4 SDRAM data I/O bit 11 ground 4 for output buffers supply voltage 5 for output buffers SDRAM data I/O bit 3 SDRAM data I/O bit 2 SDRAM data I/O bit 1 SDRAM data I/O bit 0 SDRAM data I/O bit 12 SDRAM data I/O bit 13 SDRAM data I/O bit 14 SDRAM data I/O bit 15 7 Philips Semiconductors Preliminary specification Digital camera USB interface SAA8115HL SYMBOL GND5 AGND1 ATXDP ATXDM VDDA1 RESERVED1 VDDA2 VDDA3 RESERVED2 3V3 AGND2 RESERVED3 VBUS1 VBUS2 LXDOWN AGND3 LXUP SWITCHED5V RESERVED4 RESERVED5 GND6 UCINT SUSPEND DGND4 VDDD3 GENPOR UCPOR UCCLK SCL SDA SMP CLOCKON SNAPSHOT SUSPREADYNOT TRC POR OFF M3 M2 M1 2000 Jan 27 PIN 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 TYPE(1) P P I/O I/O P - P P - I P - I I O P I O - - P O O P P I O O I I/O O O I I I O I I I I ground 5 for output buffers DESCRIPTION analog ground 1 for ATX (transceiver) positive driver of the differential data pair input/output (ATX) negative driver of the differential data pair input/output (ATX) analog supply voltage 1 for ATX test pin 1 (should not be used) analog supply voltage 2 for bandgap (reference) analog supply voltage 3 for bandgap, comparator and ring oscillator test pin 2 (should not be used) 3V3 detector input signal analog ground 2 for N-switch test pin 3 (should not be used) supply voltage input 1 from the USB supply voltage input 2 from the USB LX coil node output (5 V downconverter) analog ground 3 for N-switch LX coil node input (5 V upconverter) 5 V switched power supply test pin 4 (should not be used) test pin 5 (should not be used) ground 6 for output buffers interrupt output from USB to microcontroller control output from USB protocol hardware to microcontroller digital ground 4 for input buffers, predrivers and for the digital core digital supply voltage 3 for input buffers, predrivers and one part of the digital core Power-on reset input (for USB protocol hardware) control output from USB protocol hardware to microcontroller clock output from USB protocol hardware to microcontroller slave I2C-bus clock input slave I2C-bus data input/output switch mode power pulse output for CCD supplies control output for main oscillator switched on input for remote wake-up (snapshot) input from microcontroller for SUSPEND mode threshold control input for enabling clock 3.3 V supply domain ready indicator output disable 5 V switchable supply domain input test mode control input signal bit 3 test mode control input signal bit 2 test mode control input signal bit 1 8 Philips Semiconductors Preliminary specification Digital camera USB interface SAA8115HL SYMBOL M0 AGND4 XIN XOUT VDDA4 AGND5 VDDA5 VDDA6 REF1 REF2 REF3 RESERVED6 VGAIN LNAOUT MICIN MICSUPPLY AGND6 B4 B3 B1 B2 A1 A2 VDD6 GND7 A3 A4 Note PIN 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 TYPE(1) I P I O P P P P I I I O I O I O P O O O O O O P P O O DESCRIPTION test mode control input signal bit 0 analog ground 4 for crystal oscillator (48 MHz, 3rd overtone) oscillator input oscillator output analog supply voltage 4 for crystal oscillator (48 MHz, 3rd overtone) analog ground 5 for PLL analog supply voltage 5 for PLL analog supply voltage 6 for amplifier and ADC reference voltage 1 (used in the ADC) reference voltage 2 (used in the ADC) reference voltage 3 (used in the amplifier and the ADC) test pin 6 (should not be used) variable gain amplifier input low noise amplifier output microphone input microphone supply output analog ground 6 for amplifier and ADC vertical CCD load pulse output (VH1X) vertical CCD load pulse output (VH3X) vertical CCD load pulse output vertical CCD load pulse output vertical CCD transfer pulse output (V1X) vertical CCD transfer pulse output (V2X) supply voltage 6 for output buffers ground 7 for output buffers vertical CCD transfer pulse output (V3X) vertical CCD transfer pulse output (V4X) 1. I = input, O = output and P = power supply. 2000 Jan 27 9 Philips Semiconductors Preliminary specification Digital camera USB interface SAA8115HL handbook, full pagewidth 129 RESERVED6 133 MICSUPPLY 111 SUSPREADYNOT 110 SNAPSHOT 109 CLOCKON 108 SMP 107 SDA 106 SCL 105 UCCLK 104 UCPOR 103 GENPOR 102 VDDD3 101 DGND4 100 SUSPEND 99 UCINT 98 GND6 97 RESERVED5 96 RESERVED4 95 SWITCHED5V 94 LXUP 93 AGND3 92 LXDOWN 91 VBUS2 90 VBUS1 89 RESERVED3 88 AGND2 87 3V3 86 RESERVED2 85 VDDA3 84 VDDA2 83 RESERVED1 82 VDDA1 81 ATXDM 80 ATXDP 79 AGND1 78 GND5 77 DQ15 76 DQ14 75 DQ13 74 DQ12 73 DQ0 DQ1 72 131 LNAOUT 134 AGND6 123 AGND5 119 AGND4 126 REF1 125 VDDA6 124 VDDA5 122 VDDA4 130 VGAIN 132 MICIN 142 GND7 121 XOUT 141 VDD6 140 A2 128 REF3 127 REF2 113 POR GND4 68 C3 C2 C1 C4 SHUTTER GND1 VDD1 RG FS 1 2 3 4 5 6 7 8 9 FCDS 10 CLK1 11 DCP 12 BCP 13 VD 14 HD 15 VDD2 16 CLK2 17 GND2 18 YUV0 19 YUV1 20 YUV2 21 YUV3 22 DGND1 23 VDDD1 24 YUV4 25 YUV5 26 YUV6 27 YUV7 28 DGND2 29 LLC 30 HREF 31 VS 32 RESET 33 SNDA 34 SNCL 35 SNRES 36 VDD3 37 AD4 38 AD5 39 AD3 40 AD2 41 AD6 42 AD1 43 AD7 44 AD8 45 AD0 46 AD9 47 AD10 48 GND3 49 VDD4 50 CSB 51 RASB 52 VDDD2 53 DGND3 54 CLKEN 55 CASB 56 WEB 57 SDCLK 58 DQM 59 DQ8 60 DQ7 61 DQ9 62 DQ6 63 DQ5 64 DQ10 65 DQ4 66 DQ11 67 VDD5 69 DQ3 70 DQ2 71 SAA8115HL 112 TRC 114 OFF 120 XIN 118 M0 117 M1 116 M2 115 M3 144 A4 143 A3 139 A1 138 B2 137 B1 136 B3 135 B4 FCE350 Fig.2 Pin configuration. 2000 Jan 27 10 Philips Semiconductors Preliminary specification Digital camera USB interface 8 8.1 FUNCTIONAL DESCRIPTION Video synchronization SAA8115HL Horizontally a downsampling from 512 or 640 to either 384, 320, 192 or 160 or from 352 to 176 is necessary. The horizontal downsampling is performed with the use of a Variable Phase Delay filter (VPD-4). This filter can realize the needed downsample factors. To avoid aliasing, this module also contains a prefilter which has four modes: * No filter for medium resolution PAL (512 x 288) to CIF (352 x 288) or SIF (320 x 240) * Prefilter A (3 taps) for VGA (640 x 480) to CIF or SIF, CIF to QCIF (176 x 144) or QSIF (160 x 120) * Prefilter B (7 taps) for medium resolution PAL to QCIF or QSIF * Prefilter A combined with prefilter B-comb (13 taps) for VGA to QCIF or QSIF. Prefilter B-comb is similar to prefilter B but inserts extra taps with amplification 0. The vertical downsampling in PAL mode is from CIF to QCIF only. This is done via a vertical filter A (3 taps). In VGA mode a 4 taps polyphase filter is applied to scale from 640 x 480 to CIF and QCIF. From a full size QCIF picture a sub-QCIF (128 x 96) cut can be made. For the zoomed sub-QCIF format, the origin (upper left corner) is programmable via SNERT in 13 steps (both horizontally and vertically), so that an electronic pan and tilt is possible. The incoming 4 : 2 : 2 data is vertically filtered to 4 : 2 : 0, in order to be sent over USB, by throwing away colour samples. In the even lines the V-samples are discarded, in the odd lines the U-samples. The video synchronization module is capable of locking to the video signal implementing a horizontal gate signal HREF (HREF = HIGH when data is valid) and a VS signal indicating the start of a new video frame. 8.2 Frame rate converter and SDRAM interface An optional SDRAM (external) can be accessed using the SDRAM interface which is integrated in the SAA8115HL. Pinning and functionality is based on the NEC PD4516161 (16 Mbits) and the NEC PD4564163 (64 Mbits). When used, the memory is placed at the video input of the SAA8115HL before prefilter, scaler and compression engine. At this point only YUV 4 : 2 : 2 formatted data is available. The use of the SDRAM is twofold: * Lowering the frame rate. The memory enables to store one frame of video accumulated at a specific rate and to read it out at a lower frame rate. For interline VGA sensors, the input frame rate is either 30 fps or 15 fps. It can be lowered with a factor of 2, 3, 6, 16 or 32. For CIF or medium resolution PAL, the input frame rate is only 30 fps * Enhanced snapshot mode. Storage of full size VGA pictures in 4 : 2 : 2 format which can be retrieved upon dedicated software command. 8.3 Video formatter: downsampler and cutter This block is used to achieve the required output format from the specified sensor formats (see Fig.3). It works for YUV 4 : 2 : 2 only. In RAW mode this block is by-passed to create a full resolution snapshot. 2000 Jan 27 11 Philips Semiconductors Preliminary specification Digital camera USB interface 8.4 Compression engine SAA8115HL For a number of compression ratios, performance is also improved thanks to different quantization tables which are defined and stored in a ROM. The required table must be selected via software. Real time decoding can be done in software on any PentiumTM platform. The compression engine module (see Fig.3) can process VGA, CIF, SIF, QCIF and QSIF but has optimal performance with CIF resolution (30 fps) and VGA resolution (5 fps). The algorithm is Philips proprietary. The compression ratio is continuously programmable by setting the maximum number of bits which can be used for 4 compressed lines, a so-called band (see Table 1). It is possible to reduce the YUV input data by scaling down (divide by 2 or divide by 4 operations) to 7 or 6 bits per sample. For compression with an output rate below 2 bpp (bits per pixel) it leads to performance improvement. handbook, full pagewidth UV_EXCHANGE PAL_VGA PREFILTER_A_ON_OFF VIDEO_OUTPUT_FORMAT to transfer buffer YUV7 to YUV0 PREFILTER A PREFILTER B DOWN SCALER COMPRESSION ENGINE PREFILTER_B_ON_OFF PREFILTER B_COMB_ON_OFF COMPRESSION_MODE VP_C_ BITCOST_(MSB/LSB) FCE430 Fig.3 The video formatter and compression engine. Table 1 Data rate performed by compression engine FORMAT ADVISED DATA RATE 2 bpp 6 bpp 3 bpp 1.5 bpp 4 bpp MAXIMUM DATA RATE 12 bpp (uncompressed) uncompressed 4 bpp 3 bpp 4 bpp CIF/SIF QCIF/QSIF VGA high quality VGA RAW VGA high quality 2000 Jan 27 12 Philips Semiconductors Preliminary specification Digital camera USB interface 8.5 Transfer buffer SAA8115HL The host can synchronize on the smaller packets for the high frame rates and on the 0-length packets for the low frame rates. For every mode the FIFO must be adjusted. There are three parameters to program the video FIFO: * PACKET_SIZE (0x06): this value indicates the length of all packets with video data except for the last packet of a video frame * FIFO_OFFSET (0x04): this value indicates the number of data in the FIFO before a new packet will be transmitted over USB * READ_SPACING (0x07): this value indicates the number of 12 MHz clock cycles between read actions from the FIFO. Moreover the FIFO is enabled and disabled with FIFO_ACTIVE (0x05). The write process to the FIFO is controlled by the transfer buffer and not programmable. The read process is executed in the PSIE-MMU and is driven by the USB frame interval (1 ms). Every frame interval the PSIE-MMU tries to read PACKET_SIZE bytes from the FIFO. This read process will not be started when a new video frame is stored in the FIFO and there are less than FIFO_OFFSET bytes written. The read process stops if the next bytes are of another video frame, or if the read-pointer would overtake the write-pointer. READ_SPACING determines the read rate. Its value can easily be determined with the formula: 12000 READ_SPACING < --------------------------------------PACKET_SIZE The transfer buffer module (see Fig.4) takes care of a smooth transfer of the data to the FIFO of the USB. Moreover the transfer buffer can insert inband synchronization words in the video data stream. This function can be switched on and off with INBAND_CONTROL in register VP_TR_CONTROL (0x36). The synchronization words can only be used with non-compressed data stream and are formatted like 0x00 0xFF 0x The USB video FIFO is programmed via the I2C-bus (see Fig.5). The FIFO is designed to achieve three different packets containing video on the isochronous USB channel. Video data is contained in a chain of equally sized USB packets, except for the last packet of a video frame which is always smaller. The video frames can be separated from each other by one or more 0-length packets. For low frame rates (below 10 frames per second) there are always 0-length packets in the stream. handbook, full pagewidth data to PSIE-MMU data from transfer buffer read write FIFO read enable WRITE SYNC FIFO_OFFSET PACKET_SIZE READ_SPACING FIFO_ACTIVE FCE431 Ptr_to_start_Vframe Fig.4 USB video FIFO. 2000 Jan 27 13 Philips Semiconductors Preliminary specification Digital camera USB interface 8.7 PSIE-MMU, I2C-bus interface and USB RAM space SAA8115HL Depending on the command it is sent to the PSIE-MMU and/or to the command interpreter which configures the (de-)mux to open the path to the right register space. Subsequent write/reads to/from the data address store or retrieve data from the register space selected by the command. 8.8 ATX interface The Programmable Serial Interface Engine (PSIE) and Memory Management Unit (MMU) is the heart of the USB protocol hardware (see Fig.5). It formats the actual packets that are transferred to the USB and passes the incoming packets to the right end-point buffers. These buffers are allocated as part of the USB RAM space. The microcontroller communicates via the I2C-bus with the PSIE-MMU. The I2C-bus protocol distinguishes three register spaces. These spaces are addressed via different commands. The command is sent to the command address. The SAA8115HL contains an analog bus driver, called the ATX. It incorporates a differential and two single-ended receivers and a differential transmitter. The interface to the bus consists of a differential data pair (ATXDM and ATXDP). handbook, full pagewidth PSIE-MMU REGISTER SPACE PI_Address + 0X to/from microcontroller (DE)MUX SET MODE REGISTER SPACE I2C-BUS INTERFACE PI_Address + 10 COMMAND INTERPRETER NON USB AND VIDEO FIFO REGISTERS FCE432 to PSIE-MMU Fig.5 I2C-bus interface and register map. 8.9 Audio The SAA8115HL contains a microphone supply and an amplifier circuit composed of two stages: a Low Noise Amplifier (LNA) and a variable gain amplifier. The LNA has a fixed gain of 26 dB while the variable gain amplifier can be programmed between 0 and 30 dB by steps of 2 dB. The gain control can be done via either the SNERT interface or the I2C-bus interface (see Table 57). The serial interface must be first selected using bit SIS (see Table 57). The frequency transfer characteristic of the audio path must be controlled via external high-pass or low-pass filters. The PLL converts the 48 MHz to 256fs (fs = audio sample frequency). There are three modes for the PLL to achieve the sample frequencies of 48, 44.1 or 32 kHz (see Table 2). The bitstream ADC samples the audio signal. It runs at an oversample rate of 256 times the base sample rate. In the application, the bitstream can be converted to parallel 16-bit samples. This conversion is programmable with respect to the effective sample frequency (dropping sample results in a lower effective sample frequency) and sample resolution. As a result the effective sample rate can be determined. 2000 Jan 27 14 Philips Semiconductors Preliminary specification Digital camera USB interface Table 2 ADC clock frequencies and sample frequencies DIVIDING NUMBER 1 2 4 8 11.2996 1 2 4 8 12.2880 1 2 4 8 Note 1. Not supported. Table 3 Typical SAA8115HL compatible sensors BRAND Sony Panasonic Sharp Medium resolution PAL Sony Panasonic Sharp Toshiba CIF Other sensors Sharp ICX098AK MN3777PP and MN37771PT LZ24BP ICX054, ICX086 and ICX206 MN37210FP LZ2423B and LZ2423H TCD5391AP LZ244D and LZ2547 PART NUMBER SAMPLE ADC CLOCK FREQUENCY (MHz) (kHz) 32 16 8 note 1 44.1 22.05 11.025 5.5125 48 24 12 6 4.096 2.048 1.042 note 1 5.6448 2.8224 1.4112 0.7056 6.144 3.072 1.536 0.768 8.10 SAA8115HL Sensor pulse pattern generator CLOCK (MHz) 8.1920 The SAA8115HL incorporates a Pulse Pattern Generator (PPG) function. The PPG can be used for medium resolution PAL, CIF and VGA CCD-sensors (see Table 3). Depending on the sensor type, an external inverter driver should be required to convert the 3.3 V pulses into a voltage suitable for the used CCD-sensor. The active video size is 512 x 288 for medium resolution PAL, 352 x 288 for CIF and 640 x 480 for VGA. The total H x V size are 685 x 292 for medium resolution PAL/CIF and 823 x 486 for VGA. It should be noted that additional HD pulses are added during the vertical blanking interval to reach a total of 312 lines in PAL and CIF modes and 525 lines in VGA mode as required by the SAA8112HL. A high level of flexibility is available for the PPG thanks to 19 internal registers (see Section 9.1.3). SENSOR TYPE VGA all the sensors fully compatible with the above mentioned sensors 2000 Jan 27 15 Philips Semiconductors Preliminary specification Digital camera USB interface 8.11 Power management SAA8115HL The SAA8115HL has the feature to autonomously wake-up from SUSPEND mode, but requires microcontroller interference before going in SUSPEND mode (via the signal on pin SUSPREADYNOT). Since the main oscillator of the SAA8115HL is switched off during SUSPEND mode, precautions are needed to avoid undefined states when the clock is switched on. This is ensured via the pins CLOCKON and TRC. Pin CLOCKON goes HIGH as soon as the main oscillator is switched on. The oscillator will need some time to make a stable 48 MHz signal. However, the clock is only passed through to other parts of the SAA8115HL when the level on pin TRC reaches a certain threshold. The time needed to reach the threshold can be trimmed with an external RC circuit. 8.12 Power supply USB requires the device to switch power states. The SAA8115HL contains a power management module since the complete camera may not consume more than 500 A during the power state called SUSPEND. This requires that even the crystal oscillator must be switched off. The SAA8115HL is not functional except for some logic that enables the IC to wake-up the camera. After wake-up of the SAA8115HL first the clock to the microcontroller is generated and thereafter an interrupt is generated to wake-up the microcontroller. Therefore the clock of the microcontroller is generated by the SAA8115HL. The power management module also sets a flag in register SET_MODE_AND_READ (PSIE_MMU_STATUS). After a reset the microcontroller should check this register via the I2C-bus and find the cause of the wake-up. Different causes may require different start-up routines. The internal video processing core uses another supply domain which can be switched off during SUSPEND mode. The PPG is switched off by setting PPG_RESUME_MODE (0x08) and resetting PAL_VGA (0x09). In non CIF modes the power consumption is reduced by resetting COMPRESSION_MODE (0x2F) and COMPRESSION_CLOCK (0x09). A power supply regulator is integrated in the device. This DC-to-DC converter transforms the USB supply voltage (range from 4.0 to 5.5 V) into a stable 5 V supply voltage. This power domain is switchable. The power circuit also generates a reset signal when the external 3.3 V supply voltage is stable and in range. 2000 Jan 27 16 Philips Semiconductors Preliminary specification Digital camera USB interface 9 CONTROL REGISTER DESCRIPTION SAA8115HL This specification gives an overview of all registers. 9.1 SNERT (UART) The SAA8115HL is partly controlled via SNERT. The frame rate converter, the SDRAM interface, the video formatter, the compression engine, the PPG, the SMP and the audio functions are controlled via SNERT. This SNERT interface works independently from the frame rate and can always be operated in the full frequency range. Via SNERT the following registers are accessible (see Table 4). Table 4 SNERT write registers SAA8115HL FUNCTION write register soft reset (see Table 5) write registers Frame Rate Converter (FRC) including the SDRAM interface reserved write registers Pulse Pattern Generator (PPG) reserved write registers video formatter and compression engine reserved write registers Switch Mode Power (SMP) write register audio variable gain amplifier GENERAL REGISTER Detailed description of SNERT general register 0x00 BIT 7 X 6 X 5 X 4 X 3 X 1 0 1 0 1 0 2 1 0 reserved RESET_VP_C compression engine in reset state compression engine operating RESET_VP_VF formatter engine in reset state formatter engine operating RESET_FRC frame rate converter engine in reset state (by default) frame rate converter engine operating SNERT REGISTER 00: SOFT_RESET PARAMETER ADDRESS 00 01 to 05 06 and 07 08 to 1A 1B to 1F 20 to 38 39 to 3C 3D and 3E 3F 9.1.1 Table 5 2000 Jan 27 17 Philips Semiconductors Preliminary specification Digital camera USB interface 9.1.2 Table 6 FRAME RATE CONVERTER AND SDRAM INTERFACE REGISTERS Detailed description of SNERT FRC and SDRAM register 0x01 BIT 7 X X X X 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 Table 7 6 5 4 3 2 1 0 reserved SAA8115HL SNERT REGISTER 01: FRC_CONTROL_0 PARAMETER number of active lines after rising edge of VS signal; range: 0 to 6 (by default 0) FRAMERATE_DIVIDER_SELECT_BIT undefined 32 (30 fps in; 0.9375 fps out) 16 (15 fps in; 0.9375 fps out) 6 (30 fps in; 5 fps out) 3 (30 fps in; 10 fps out) or (15 fps in; 5 fps out) 2 (30 fps in; 15 fps out) or (15 fps in; 7.5 fps out) 1 (1 fps in; 1 fps out) (by default) undefined LLC_CLKFREQ 24 MHz (by default) 12 MHz Detailed description of SNERT FRC and SDRAM register 0x02 BIT SNERT REGISTER 02: FRC_CONTROL_1 2 1 0 reserved REFRESH_MODE 1 0 X X 1 1 0 0 1 0 1 0 automatic SRAM refresh precharge command as implicit refresh (by default) REFRESH_CLOCK (MSBs) see Table 9 INPUT_FORMAT undefined medium resolution CIF VGA (by default) PARAMETER 7 X 6 X 5 X 4 3 2000 Jan 27 18 Philips Semiconductors Preliminary specification Digital camera USB interface Table 8 Detailed description of SNERT FRC and SDRAM register 0x03 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 95 for PAL sensors 159 for VGA sensors (by default) 63 for CIF sensors Table 9 Detailed description of SNERT FRC and SDRAM register 0x04 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 246 for PAL sensors 395 for VGA sensors (by default) 239 for CIF sensors Table 10 Detailed description of SNERT FRC and SDRAM register 0x05 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X number of lines in a frame 243 for VGA sensors (by default) 146 for PAL or CIF sensors SAA8115HL SNERT REGISTER 03: FRC_ROWWIDTH PARAMETER X specifies the width of the row of the SDRAM SNERT REGISTER 04: FRC_REFRESH_LSB PARAMETER X specifies the number of clock cycles between two refresh cycles SNERT REGISTER 05: FRC_STOPWRITE PARAMETER 2000 Jan 27 19 Philips Semiconductors Preliminary specification Digital camera USB interface 9.1.3 PULSE PATTERN GENERATOR REGISTERS SAA8115HL Table 11 Detailed description of SNERT PPG register 0x08 BIT 7 X 6 X 5 X 1 0 1 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 X 1 0 1 0 1 1 4 3 2 1 0 reserved SHUTTER_UPDATE_BUFFER during the vertical blanking (shutter speed is buffered) immediately (by default) PPG_RESUME_MODE switched off (except vertical transfer pulses in case of VGA sensors) operating (by default) PPG _FRAMERATE undefined 5 fps 10 fps 15 fps 20 fps 24 fps 30 fps (by default) SNERT REGISTER 08: PPG_CONTROL_0 PARAMETER 2000 Jan 27 20 Philips Semiconductors Preliminary specification Digital camera USB interface Table 12 Detailed description of SNERT PPG register 0x09 BIT 7 X 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 X 1 1 0 0 1 1 0 0 1 1 0 0 X 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 X 1 0 6 5 4 3 2 1 0 reserved COMPRESSION_CLOCK reserved 24 MHz 19.2 MHz 16 MHz 12 MHz (by default) 9.6 MHz 8.0 MHz 6.0 MHz 4.8 MHz 4.0 MHz 2.4 MHz 2.0 MHz off VGA_SENSOR_TYPE (valid if MSB set to logic 0) VGA (Sony and Panasonic) VGA (Sharp) reserved PAL_VGA PAL or CIF timing VGA timing (by default) SAA8115HL SNERT REGISTER 09: PPG_CONTROL_1 PARAMETER 2000 Jan 27 21 Philips Semiconductors Preliminary specification Digital camera USB interface Table 13 Detailed description of SNERT PPG register 0x0A BIT 7 X 1 0 1 1 0 0 0 0 X X 1 1 0 0 1 0 1 0 1 0 1 1 0 0 0 0 Note 1. If bits [5 to 3] equal bits [2 to 0] then FH2 is the inverse of FH1. X X 1 1 0 0 1 0 1 0 1 0 6 5 4 3 2 1 0 reserved RG_SHORT RG pulse width is set to half of nominal value RG pulse width is set to nominal value FH2_CTRL (non FT mode); note 1 no horizontal blanking no horizontal blanking, pulse inverted blanked to HIGH, starts HIGH blanked to LOW, starts LOW blanked to LOW, starts HIGH blanked to HIGH, starts LOW FH1_CTRL (non FT mode); note 1 no horizontal blanking, pulse inverted no horizontal blanking blanked to HIGH, starts LOW blanked to HIGH, starts HIGH blanked to HIGH, starts LOW blanked to LOW, starts HIGH SNERT REGISTER 0A: PPG_H_CTRL PARAMETER SAA8115HL 2000 Jan 27 22 Philips Semiconductors Preliminary specification Digital camera USB interface Table 14 Detailed description of SNERT PPG register 0x0B BIT 7 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 5 4 3 2 1 0 A4_INV positive pulses negative pulses A3_INV positive pulses negative pulses A2_INV negative pulses positive pulses A1_INV negative pulses positive pulses B4_INV positive pulses negative pulses B3_INV positive pulses negative pulses B2_INV negative pulses positive pulses B1_INV negative pulses positive pulses SNERT REGISTER 0B: PPG_V_INV PARAMETER SAA8115HL 2000 Jan 27 23 Philips Semiconductors Preliminary specification Digital camera USB interface Table 15 Detailed description of SNERT PPG register 0x0C BIT 7 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 5 4 3 2 1 0 CLK2_INV inverted pulses nominal pulses CLK1_INV inverted pulses nominal pulses FS_INV positive pulses negative pulses FCDS_INV positive pulses negative pulses FR_INV positive pulses negative pulses C3_INV negative pulses positive pulses C2_INV negative pulses positive pulses C1_INV negative pulses positive pulses SNERT REGISTER 0C: PPG_H_INV PARAMETER SAA8115HL 2000 Jan 27 24 Philips Semiconductors Preliminary specification Digital camera USB interface Table 16 Detailed description of SNERT PPG register 0x0D BIT 7 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 5 4 3 2 1 0 SELECT_A2 A2 is HIGH during read-out gate in line 2 A2 is LOW during read-out gate in line 2 SELECT_A3 A3 equals A4 (in case of VGA type 1 sensors) A3 equals A2 C4_INV negative pulses positive pulses CR_INV positive pulses negative pulses BCP_INV negative pulses positive pulses DCP_INV negative pulses positive pulses HD_INV negative pulses positive pulses VD_INV negative pulses positive pulses SNERT REGISTER 0D: PPG_MISC_INV PARAMETER SAA8115HL Table 17 Detailed description of SNERT PPG register 0x0E BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of line number (9 bits) SNERT REGISTER 0E: PPG_SHUTTERSPEED_V_LSB PARAMETER Table 18 Detailed description of SNERT PPG register 0x0F BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) SNERT REGISTER 0F: PPG_SHUTTERSPEED_H_LSB PARAMETER 2000 Jan 27 25 Philips Semiconductors Preliminary specification Digital camera USB interface Table 19 Detailed description of SNERT PPG register 0x10 BIT 7 X 6 X 5 X 4 X 1 0 X X 3 2 1 0 reserved SENSOR_TYPE Sony Sharp MSBs of pixel number (10 bits) X MSBs of line number (9 bits) Table 20 Detailed description of SNERT PPG register 0x11 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SAA8115HL SNERT REGISTER 10: PPG_SHUTTERSPEED_MSB PARAMETER SNERT REGISTER 11: PPG_BCP_START_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where BCP starts Table 21 Detailed description of SNERT PPG register 0x12 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 12: PPG_BCP_STOP_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where BCP stops Table 22 Detailed description of SNERT PPG register 0x13 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 13: PPG_DCP_START_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where DCP starts Table 23 Detailed description of SNERT PPG register 0x14 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 14: PPG_DCP_STOP_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where DCP stops Table 24 Detailed description of SNERT PPG register 0x15 BIT 7 X 6 X X X X X X 5 4 3 2 1 0 MSBs of PPG_DCP_STOP MSBs of PPG_DCP_START MSBs of PPG_BCP_STOP X MSBs of PPG_BCP_START SNERT REGISTER 15: PPG_BCP_DCP_MSB PARAMETER 2000 Jan 27 26 Philips Semiconductors Preliminary specification Digital camera USB interface Table 25 Detailed description of SNERT PPG register 0x16 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SAA8115HL SNERT REGISTER 16: PPG_B3_START_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where B3 starts Table 26 Detailed description of SNERT PPG register 0x17 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 14: PPG_B3_STOP_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where B3 stops Table 27 Detailed description of SNERT PPG register 0x18 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 18: PPG_B4_START_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where B4 starts Table 28 Detailed description of SNERT PPG register 0x19 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 19: PPG_B4_STOP_LSB PARAMETER X 8 LSBs of pixel number (10 bits) where B4 stops Table 29 Detailed description of SNERT PPG register 0x1A BIT 7 X 6 X X X X X X 5 4 3 2 1 0 MSBs of PPG_B4_STOP MSBs of PPG_B4_START MSBs of PPG_B3_STOP X MSBs of PPG_B3_START SNERT REGISTER 1A: PPG_B3_B4_MSB PARAMETER 2000 Jan 27 27 Philips Semiconductors Preliminary specification Digital camera USB interface 9.1.4 VIDEO FORMATTER AND COMPRESSION ENGINE REGISTERS SAA8115HL Table 30 Detailed description of SNERT video formatter register 0x20 BIT 7 X 6 X X 1 1 0 0 1 0 1 0 1 0 1 0 1 0 5 4 3 2 1 0 reserved UV_EXCHANGE exchange chrominance irregularities if needed SCALE_DATA: limits the number of bits of the video signal undefined 6 bits 7 bits 8 bits PREFILTER_B_COMB_ON_OFF (if filter B is on) prefilter B_COMB with 13 taps prefilter B_COMB with 7 taps PREFILTER_B_ON_OFF on with 7 taps bypassed PREFILTER_A_ON_OFF on with 3 taps bypassed SNERT REGISTER 20: VP_VF_CONTRL_0 PARAMETER 2000 Jan 27 28 Philips Semiconductors Preliminary specification Digital camera USB interface Table 31 Detailed description of SNERT video formatter register 0x21 BIT 7 1 0 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 6 5 4 3 2 1 0 throw away samples average UV samples VGA_RAW: data mode raw data, no scaling or 4 : 2 : 0 formatting YUV data VIDEO_OUTPUT_FORMAT undefined SIF QSIF undefined VGA CIF QCIF sub-QCIF VIDEO_INPUT_FORMAT undefined square SIF (sensors with square pixels) CIF (sensors with 12/11 pixel ratio format) medium resolution PAL undefined undefined undefined VGA SAA8115HL SNERT REGISTER 21: VP_VF_CONTRL_1 PARAMETER 420_FIL_BYPASS: 4 : 2 : 0 formatter mode Table 32 Detailed description of SNERT video formatter register 0x22 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 0 phase 0 SNERT REGISTER 22: VP_VF_VCOEF_C0_0 PARAMETER Table 33 Detailed description of SNERT video formatter register 0x23 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 0 phase 1 SNERT REGISTER 23: VP_VF_VCOEF_C0_1 PARAMETER 2000 Jan 27 29 Philips Semiconductors Preliminary specification Digital camera USB interface Table 34 Detailed description of SNERT video formatter register 0x24 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 0 phase 2 SAA8115HL SNERT REGISTER 24: VP_VF_VCOEF_C0_2 PARAMETER Table 35 Detailed description of SNERT video formatter register 0x25 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 1 phase 0 SNERT REGISTER 25: VP_VF_VCOEF_C1_0 PARAMETER Table 36 Detailed description of SNERT video formatter register 0x26 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 1 phase 1 SNERT REGISTER 26: VP_VF_VCOEF_C1_1 PARAMETER Table 37 Detailed description of SNERT video formatter register 0x27 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 1 phase 2 SNERT REGISTER 27: VP_VF_VCOEF_C1_2 PARAMETER Table 38 Detailed description of SNERT video formatter register 0x28 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 2 phase 0 SNERT REGISTER 28: VP_VF_VCOEF_C2_0 PARAMETER Table 39 Detailed description of SNERT video formatter register 0x29 BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 2 phase 1 SNERT REGISTER 29: VP_VF_VCOEF_C2_1 PARAMETER 2000 Jan 27 30 Philips Semiconductors Preliminary specification Digital camera USB interface Table 40 Detailed description of SNERT video formatter register 0x2A BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 2 phase 2 SAA8115HL SNERT REGISTER 2A: VP_VF_VCOEF_C2_2 PARAMETER Table 41 Detailed description of SNERT video formatter register 0x2B BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 3 phase 0 SNERT REGISTER 2B: VP_VF_VCOEF_C3_0 PARAMETER Table 42 Detailed description of SNERT video formatter register 0x2C BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 3 phase 1 SNERT REGISTER 2C: VP_VF_VCOEF_C3_1 PARAMETER Table 43 Detailed description of SNERT video formatter register 0x2D BIT 7 X X X X X X X 6 5 4 3 2 1 0 reserved X vertical filter coefficient tap 3 phase 2 SNERT REGISTER 2D: VP_VF_VCOEF_C3_2 PARAMETER Table 44 Detailed description of SNERT video formatter register 0x2E BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 2E: VP_VF_LIMITER PARAMETER X output of the video formatter is clipped to this maximum value 2000 Jan 27 31 Philips Semiconductors Preliminary specification Digital camera USB interface Table 45 Detailed description of SNERT compression engine register 0x2F BIT 7 X X X X X 1 1 0 0 1 0 1 0 1 0 6 5 4 3 2 1 0 reserved QTABLE_SELECT: quantization table select range [0 : 15] DC_COEFF_LENGTH undefined 8 bits 7 bits 6 bits COMPRESSION_MODE on off (by default) SAA8115HL SNERT REGISTER 2F: VP_VF_CONTROL PARAMETER Table 46 Detailed description of SNERT compression engine register 0x30 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 30: VP_C_YMASK PARAMETER X operates an AND between this value and the compression engine input; can be used to set bit positions in the Y signal to 0 (by default 0x00) Table 47 Detailed description of SNERT compression engine register 0x31 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 31: VP_C_UVMASK PARAMETER X operates an AND between this value and the compression engine input; can be used to set bit positions in the UV signal to 0 (by default 0x00) Table 48 Detailed description of SNERT compression engine register 0x32 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 32: VP_C_BITCOST_MSB PARAMETER X set the compression ratio; the bitcost determines the maximum number of bits generated by the compression algorithm for 4 subsequent lines Table 49 Detailed description of SNERT compression engine register 0x33 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 33: VP_C_BITCOST_LSB PARAMETER X set the compression ratio; the bitcost determines the maximum number of bits generated by the compression algorithm for 4 subsequent lines 2000 Jan 27 32 Philips Semiconductors Preliminary specification Digital camera USB interface Table 50 Detailed description of SNERT compression engine register 0x34 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SAA8115HL SNERT REGISTER 34: VP_C_THRESHOLD_MSB PARAMETER X output of the video formatter is clipped to this maximum value Table 51 Detailed description of SNERT compression engine register 0x35 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 35: VP_C_THRESHOLD_LSB PARAMETER X threshold must be set to: (number of UV blocks per band) x (DC_COEFF_LENGTH + 2) Table 52 Detailed description of SNERT compression engine register 0x36 BIT 7 X 1 0 1 0 6 5 4 3 2 1 0 reserved VGA_FORMAT 4 : 2 : 2 (uncompressed only) 4:2:0 INBAND_CONTROL on off LLC_OUT_DIV: select the rate at which the video data is transmitted to the USB core X X X X X range [1 to 31] SNERT REGISTER 36: VP_TR_CONTROL PARAMETER Table 53 Detailed description of SNERT compression engine register 0x37 BIT 7 X 6 X 5 X 4 X X X X X 3 2 1 0 VERTICAL_OFFSET range 3 x [0 to 15] HORIZONTAL_OFFSET range 4 x [0 to 12] SNERT REGISTER 37: VP_TR_SQCIF_OFFSET PARAMETER Table 54 Detailed description of SNERT compression engine register 0x38 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 38: VP_VS_V_SHIFT PARAMETER X shift internal line counter with respect to VS pulse 2000 Jan 27 33 Philips Semiconductors Preliminary specification Digital camera USB interface 9.1.5 SWITCH MODE POWER REGISTERS SAA8115HL Table 55 Detailed description of SNERT SMP register 0x3D BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 3D: SMP_PERIOD PARAMETER X period of SMP signal in units of 4 x XOSC_PERIOD (0 by default) Table 56 Detailed description of SNERT SMP register 0x3E BIT 7 X 9.1.6 6 X 5 X 4 X 3 X 2 X 1 X 0 SNERT REGISTER 3E: SMP_LOWTIME PARAMETER X low edge of SMP signal in units of 4 x XOSC_PERIOD (0 by default) AUDIO VARIABLE GAIN AMPLIFIER Table 57 Detailed description of SNERT audio gain amplifier register 0x3F BIT 7 X 6 X 1 0 X X X X 5 4 3 2 1 0 reserved SIS: serial interface select SNERT I2C-bus reserved X variable gain settings (0 to 30 dB) SNERT REGISTER 3F: AUDIO_VGAIN PARAMETER 2000 Jan 27 34 Philips Semiconductors Preliminary specification Digital camera USB interface 9.2 I2C-bus interface SAA8115HL The USB function has its own I2C-bus interface for communication with the microcontroller. The I2C-bus uses two addresses: * Command address for writing commands to the Memory Manager (MM) * Data address for writing/reading data to/from the Memory Manager (MM). An address is a byte. The 7 MSBs are the actual address, the LSB is the R/W bit. When it is logic 0, data is transferred from the master to the slave, when it is logic 1, data is written from the slave to the master. The 6 MSBs of the two addresses are equal and are defined by the PI_Address = 010111 (see Table 58). The LSB of the address differentiates between the command address and the data address. When bit 1 is logic 1 the address is the command address (0x5E) and when bit 1 is logic 0 the address is one of the data addresses (0x5C or 0x5D). Table 58 I2C-bus addresses BIT ADDRESS 7 0 0 0 0 9.2.1 6 1 1 1 1 5 0 0 0 0 4 1 1 1 1 3 1 1 1 1 2 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0x5C: for writing data to the memory manager 0x5D: for reading data from the memory manager 0x5E: for writing commands 0x5F: not in use COMMANDS The commands listed in Table 59 must be sent to the I2C-bus address 0x5E. Table 59 I2C-bus USB command codes BIT FUNCTION 7 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 6 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 select end-point read/write status initialize/read status information read/write register bank X 0 0 1 0 0 0 1 0 1 1 not used set non-USB register read/write data acknowledge setup set buffer empty set buffer full read interrupt register read current frame number send resume set status change bits set mode end-point number end-point number end-point number 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0 address X 0 0 0 0 0 1 1 1 1 0 X 0 0 0 1 1 0 0 1 1 1 2000 Jan 27 35 Philips Semiconductors Preliminary specification Digital camera USB interface Table 60 Detailed description of set mode and write register overview BYTE 3 SET_MODE_AND_WRITE SAA8115HL N1 timer: programmable timer for power management; counts 12 MHz cycles; must be bigger than number of cycles needed for the microcontroller to go in power-down state after pin SUSPREADYNOT is made LOW N2 timer: programmable timer for power management; counts 12 MHz cycles; determines the time between the microcontroller clock is switched off and the main clock is switched off PSIE-MMU control byte (see Table 61) 2 1 Table 61 Detailed description of set mode and write byte 3 BIT 7 X 6 X 5 X 1 4 3 2 1 0 reserved interrupt after isochronous audio transfer for each isochronous audio transfer an interrupt to the microcontroller will be generated; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8115HL no interrupts are given to the microcontroller interrupt after isochronous video transfer 1 for each isochronous video transfer an interrupt to the microcontroller will be generated; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8115HL no interrupts are given to the microcontroller audio end-point 1 0 audio end-point enabled; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8115HL audio end-point disabled; the PSIE-MMU will not react on in-tokens on the audio end-point video end-point 1 0 video end-point enabled; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8115HL video end-point disabled; the PSIE-MMU will not react on in-tokens on the video end-point error debug mode 1 interrupts are generated only in the event the transfer is not successfully completed; the microcontroller can read data from the interrupt and status registers to see the cause of this error all successful USB transactions are reported to the microcontroller via an interrupt; default set to logic 0 upon general power-on reset by the SAA8115HL PSIE-MMU CONTROL BYTE PARAMETER 0 0 0 2000 Jan 27 36 Philips Semiconductors Preliminary specification Digital camera USB interface Table 62 Detailed description of set mode and read status byte BIT 7 X 6 X 5 X 4 X 1 0 1 0 1 0 1 0 9.2.2 END-POINTS 3 2 1 0 reserved remote wake-up status flag remote wake-up when device is in SUSPEND mode no remote wake-up resume status flag PSIE-MMU STATUS BYTE PARAMETER SAA8115HL bus resume by the host when device is in SUSPEND mode no bus resume bus reset status flag bus reset no bus reset power-up status flag general power-up reset no power-up reset The SAA8115HL has 6 logical end-points which are listed in Table 63. Table 63 Mapping of logical to physical end-point numbers for used end-points END-POINT NAME Control end-point Control end-point Interrupt end-point Interrupt end-point Iso video end-point Iso video end-point LOGICAL END-POINT 0 1 2 3 4 5 PHYSICAL END-POINT BUFFER SIZE OUT 8 8 8 8 96.0 35.1 0 2 - - - - IN 1 3 4 5 6 7 2000 Jan 27 37 Philips Semiconductors Preliminary specification Digital camera USB interface 9.2.3 CONTROL TOP REGISTERS SAA8115HL The following registers can be written on I2C-bus address 1 after the command 0xE8 on I2C-bus address 0. Table 64 I2C-bus control top registers ADDRESS 0x08 0x09 0x0A 0x0B clock control reset control mux block control power-on analog modules control CONTROL TOP REGISTERS (BASE ADDRESS: 0x08) Table 65 Detailed description of I2C-bus control top registers 0x08 BIT 7 1 0 0 0 1 1 0 1 0 1 X 1 0 1 0 1 0 X 6 5 4 3 2 1 0 select ADC clock source sel_ad: clock generated from ADC sel_pll: clock generated from PLL set clock dividers for ADC set_divide00: divided by 1 set_divide01: divided by 2 set_divide10: divided by 4 set_divide11: divided by 8 reserved disable 48 MHz clock dis_clk_48: disable 48 MHz clock enable clock disable receiver clock dis_clk_rec: disable receiver clock enable clock disable ADC clock dis_clk_ad: disable ADC clock enable clock reserved TOP REGISTER 0x08: CLKSHOP_CONTROL PARAMETER 2000 Jan 27 38 Philips Semiconductors Preliminary specification Digital camera USB interface Table 66 Detailed description of I2C-bus control top registers 0x09 BIT 7 0 0 1 1 6 0 1 0 1 X X 1 0 X 1 0 1 0 5 4 3 2 1 0 set PLL frequency fcode00: 256 x 44.1 kHz fcode01: 256 x 32 kHz fcode10: 256 x 48 kHz fcode11: 256 x 44.1 kHz reserved reset PSIE-MMU top module SAA8115HL TOP REGISTER 0x09: RST_GEN AND PLL_CONTROL PARAMETER upc_rst_mmu: resetting the USB protocol block (called PSIE-MMU) during tests or in case of errors no reset reserved reset ADIF top module upc_rst_adif: resetting the digital audio part during tests or in case of errors no reset reset AGC module upc_rst_AGC: resetting the AGC control during tests or in case of errors no reset Table 67 Detailed description of I2C-bus control top registers 0x0A BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X reserved TOP REGISTER 0x0A: IO_MUX_CONTROL PARAMETER 2000 Jan 27 39 Philips Semiconductors Preliminary specification Digital camera USB interface Table 68 Detailed description of I2C-bus control top registers 0x0B BIT 7 1 0 1 0 1 0 X 1 0 1 0 1 0 1 0 6 5 4 3 2 1 0 SAA8115HL TOP REGISTER 0x0B: POWER_CONTROL_OF_ANALOG_MODULES PARAMETER power control oscillator module upc_osc_off: power management 48 MHz enabled power management 48 MHz disabled power control audio module upc_osc_ad_off: power management audio enabled power management audio disabled power control PLL module upc_pll_off: PLL power-off power-on reserved power control ADC module left channel upc_adl_off: power-off power-on power control ADC module right channel upc_adr_off: power-off power-on power control AGC module left channel upc_AGCl_off: power-off power-on power control AGC module right channel upc_AGCr_off: power-off power-on 2000 Jan 27 40 Philips Semiconductors Preliminary specification Digital camera USB interface 9.2.4 VIDEO FIFO REGISTERS SAA8115HL Table 69 I2C-bus video FIFO registers overview ADDRESS 0x04 0x05 0x06 0x07 FIFO offset (8 LSBs) FIFO active and FIFO offset (3 MSBs) packet size (8 LSBs) read spacing and packet size (2 MSBs) VIDEO FIFO REGISTERS (BASE ADDRESS: 0x04) Table 70 Detailed description of I2C-bus video FIFO registers 0x04 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 FIFO_OFFSET X mode_fifo_offset: sets the minimum contents of the FIFO that has to be reached, before a new video frame will be put on the USB. This value can be set between 0 and 2047. Total 11 bits with 8 LSBs in this register and 3 MSBs in register 0x05. FIFO REGISTER 0x04: FIFO_OFFSET PARAMETER Table 71 Detailed description of I2C-bus video FIFO registers 0x05 BIT 7 1 0 X X X X X X X 6 5 4 3 2 1 0 FIFO_ACTIVE mode_active: FIFO is active and the contents of the other mode registers should not be updated by the microcontroller (maledictive) FIFO not active reserved FIFO_OFFSET (MSBs) 3 MSBs of the offset value; see also register 0x04 FIFO REGISTER 0x05: FIFO_ACTIVE AND FIFO_OFFSET PARAMETER 2000 Jan 27 41 Philips Semiconductors Preliminary specification Digital camera USB interface Table 72 Detailed description of I2C-bus video FIFO registers 0x06 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 PACKET_SIZE X SAA8115HL FIFO REGISTER 0x06: PACKET_SIZE PARAMETER mode_packet_size: sets the packet size of the USB video channel. Packets can vary in size between 0 and 1023. Total 10 bits with 8 LSBs in this register and 2 MSBs in register 0x07. Table 73 Detailed description of I2C-bus video FIFO registers 0x07 BIT 7 X 6 X 5 X 4 X 3 X 2 X 1 0 READ_SPACING mode_read_spacing: sets the periodicity of the read pulses; the periodicity can be set from 1 to 63 (from `000001' to `111111') PACKET_SIZE X X mode_packet_size: 2 MSBs of the value (8 LSBs in register 0x06) FIFO REGISTER 0x07: READ_SPACING AND PACKET_SIZE PARAMETER 2000 Jan 27 42 Philips Semiconductors Preliminary specification Digital camera USB interface 9.2.5 ADIF TOP REGISTERS SAA8115HL Table 74 I2C-bus ADIF top registers overview ADDRESS 0x0C 0x0D 0x0E 0x0F reserved reserved VGA control gain ADIF control (ADIF2MMU) ADIF TOP REGISTERS (BASE ADDRESS: 0x0C) Table 75 Detailed description of I2C-bus ADIF top registers 0x0E BIT 7 X 0 1 X X 0 0 : 0 1 0 0 : 1 1 0 0 : 1 1 0 1 : 1 1 6 5 4 3 2 1 0 reserved GAIN_SOURCE_SELECT reserved gain is controlled directly by bits 3 to 0 reserved GAIN_CONTROL; 0 to 30 dB in steps of 2 dB 0 dB 2 dB : 28 dB 30 dB ADIF REGISTER 0x0E: GAIN_CONTROL PARAMETER 2000 Jan 27 43 Philips Semiconductors Preliminary specification Digital camera USB interface Table 76 Detailed description of I2C-bus ADIF top registers 0x0F BIT 7 X 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 6 5 4 3 2 1 0 reserved number of bytes per sample 0 (reserved) 1 (8 bits audio samples) 2 (16 bits audio samples) 3 (24 bits audio samples) selection mono/stereo operation mono stereo selection input for ADC path (ADIF mux) digital input (from I2S-bus) analog input (from Vin_left and Vin_right) SAA8115HL ADIF REGISTER 0x0F: ADIF_CONTROL PARAMETER selection high-pass filter (DC filter) for ADC down sample filter high-pass filter off high-pass filter on selection audio serial input format I2S-bus LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits 2000 Jan 27 44 Philips Semiconductors Preliminary specification Digital camera USB interface 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDA VDDA_USB VDDD Vn PARAMETER analog supply voltage analog supply voltage from USB digital supply voltage voltage on pins AGND and DGND all other pins Tstg Tamb Tj Note 1. This concerns pins VBUS1 and VBUS2. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 45 storage temperature ambient temperature junction temperature -0.5 -0.5 -55 0 -40 note 1 CONDITIONS -0.5 -0.5 -0.5 MIN. SAA8115HL MAX. +4.0 +5.5 +4.0 +4.0 VDD + 0.5 +150 70 +125 UNIT V V V V V C C C UNIT K/W 12 CHARACTERISTICS VDDD = VDDA = 3.3 V 10%; Tamb = 0 to 70 C. SYMBOL Supplies VDDDn VDDAn VDDA_USB VDGND VAGND IDDDn IDDAn VIL VIH VOL VOH digital supply voltage analog supply voltage analog supply voltage from USB digital ground supply analog ground supply digital supply current analog supply current Tamb = 25 C Tamb = 25 C note 1 3.0 3.0 4.0 -0.3 -0.3 - - - 2.0 0 0.9VDDD 3.3 3.3 5.0 0.0 0.0 - - - - - - 3.6 3.6 5.5 +0.3 +0.3 tbf tbf V V V V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Data and control inputs LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage 0.8 - V V Data and control outputs 0.1VDDD V VDDD V 2000 Jan 27 45 Philips Semiconductors Preliminary specification Digital camera USB interface SAA8115HL SYMBOL Microphone supply IDD0 Vref VO IO PARAMETER CONDITIONS - at 12VDDA VDDA = 3.3 V - - - MIN. TYP. MAX. UNIT supply current input reference voltage output voltage output current 0.85 1.65 3.0 - 1.2 - - 2.0 mA V V mA Low noise amplifier TRANSFER FUNCTION Ri IDD1 A Vo(rms) THD VOO1 BIASING Iref1 input impedance supply current amplification output voltage (RMS value) total harmonic distortion output offset voltage note 2 3.5 - 27 - - - - 5.0 0.85 28 - -69 0.0 - 1.2 29 800 -63 1.0 - k mA dB mV dB mV A reference current 10 Variable gain amplifier TRANSFER FUNCTION Ri IDD2 A THD VOO2 BIASING Iref2 Audio PLL fi(clk) fo(clk) B input impedance supply current amplification total harmonic distortion output offset voltage note 3 note 4 A = 0 dB A = 30 dB 7.0 - 0.0 - - - - - - note 5 - - - 10.5 0.45 - -88 -65 1.0 14 13 0.6 32 -82 -57 2.0 30 - - - - k mA dB dB dB mV mV A MHz MHz kHz reference current 10 clock input frequency clock output frequency bandwidth damping 48 2.3 0.98 11.2996 - Audio ADC ( converter) INPUTS fi Vi(rms) N Nbit input signal frequency input voltage (RMS value) order of the number of output bits 1 - - - - 800 20 - - - kHz mV TRANSFER FUNCTION 3 1 2000 Jan 27 46 Philips Semiconductors Preliminary specification Digital camera USB interface SAA8115HL SYMBOL Nbit(eq) DRi fclk THD PARAMETER equivalent output resolution (bit) dynamic range at input clock frequency clock frequency duty factor total harmonic distortion CONDITIONS - note 6 - - - - MIN. TYP. 16 96.6 - 50 -70 - - MAX. UNIT dB MHz % dB 5.6448 - -55 ATX transceiver DRIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM fo(sample) tr tf tmatch Vcr Zo fi(sample) fi(D) tframe sample output frequency rise transition time fall transition time transition time matching output signal crossover voltage driver output impedance CL = 50 pF CL = 50 pF note 7 4 4 4 90 1.3 steady state drive 30 - - - - - - - 12.00 1.000 48 20 20 110 2.0 42 kHz ns ns % V kHz Mbits/s ms RECEIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM sample input frequency data input frequency rate frame interval 5 - - 55 - - DC-to-DC converter 5 V UP AND DOWN CONVERTER (SWITCHABLE SUPPLY DOMAIN) VO Vripple IL RDSON_P1 RDSON_N1 RDSON_P2 RDSON_N2 output voltage ripple on output voltage load current PMOS switch-on resistance; down converter NMOS switch-on resistance; down converter PMOS switch-on resistance; up converter NMOS switch-on resistance; up converter note 8 note 8 note 8 note 8 4.9 - - - - - - 5.0 20 - 1.0 4.5 1.1 4.6 5.1 - 150 - - - - V mV mA 2000 Jan 27 47 Philips Semiconductors Preliminary specification Digital camera USB interface Notes 1. This concerns pins VBUS1 and VBUS2. 2. The distortion is measured at 1 kHz, Vo(rms) = 600 mV. 3. The distortion is measured at 1 kHz, Vo(rms) = 600 mV and A = 0 dB. 4. The distortion is measured at 1 kHz, Vo(rms) = 600 mV and A = 30 dB. 5. Frequencies depend on PLL settings (see Table 2). input voltage 6. Defined here as: 20 x log -----------------------------------------------------------------------------equivalent input noise voltage tr 7. Transition time matching: t match = -- x 100% tf 8. Including metal and contact resistance on chip and bonding wire resistance. SAA8115HL 2000 Jan 27 48 Philips Semiconductors Preliminary specification Digital camera USB interface 13 TIMING VDDD = VDDA = 3.3 V 10%; Tamb = 0 to 70 C. SYMBOL PARAMETER CONDITIONS MIN. SAA8115HL TYP. MAX. UNIT Data input related to LLC (see Fig.6) PINS YUV0 TO YUV7, HREF, VS tsu(i)(D) th(i)(D) td1 td2 td3 td4 td5 td6 td7 td8 tWH(C1) tWL(C2) tWL(FCDS) tWL(FS) tWL(RG) tWL(CLK1) tWH(CLK2) tr data input set-up time data input hold time 5 3 -3.5 0 20.5 21.5 0 0 2.5 1 80 84 17 41 42 84 39 note 1 - - - - - note 1 - - - - - 4 4 4 4 4 - - - - - ns ns ns ns ns 4 4 4 4 4 - - - - - ns ns ns ns ns - - -2.5 1.5 21.5 22.5 1.5 0.5 3.0 1.5 81 85 18.5 42 43 84.5 40 - - -1.5 3 22.5 23.5 3 2 3.5 2 - - - - - - - ns ns PPG high-speed pulses for Sony ICX098AK VGA CCD-sensor (see Fig.7) delay between falling edge C2 and rising edge C1 delay between rising edge C2 and falling edge C1 delay between falling edge C1 and rising edge FCDS delay between rising edge C1 and rising edge FS delay between rising edge C1 and falling edge RG delay between falling edge CLK1 and rising edge C1 delay between rising edge CLK1 and falling edge C1 delay between rising edge CLK2 and rising edge C1 C1 pulse width HIGH C2 pulse width LOW FCDS pulse width LOW FS pulse width LOW RG pulse width LOW CLK1 pulse width LOW CLK2 pulse width HIGH rise time pulse C1 pulse C2 pulse RG pulse FCDS pulse FS tf fall time pulse C1 pulse C2 pulse RG pulse FCDS pulse FS Note 1. CL = 11 pF; Tamb = 25 C. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2000 Jan 27 49 Philips Semiconductors Preliminary specification Digital camera USB interface SAA8115HL handbook, full pagewidth LLC tsu(i)D th(i)D data input FCE606 Fig.6 Data input timing. handbook, full pagewidth tWH(C1) 50% td1 50% td2 50% tWL(C2) 50% C1 C2 50% FCDS 50% 50% tWL(FCDS) td3 50% tWL(FS) 50% td4 FS td5 RG 50% td6 CLK1 50% tWL(RG) 50% td7 50% tWL(CLK1) td8 CLK2 50% tWH(CLK2) 50% FCE607 Fig.7 PPG high-speed pulses for Sony ICX098AK VGA CCD-sensor. 2000 Jan 27 50 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... andbook, full pagewidth DATA7 to DATA0 PSEN ALE AD10 to AD8 AD15 to AD11 SDAE SCLE SCL SDA YUV7 to YUV0 HREF VS LLC HD VD CLK1 CLK2 SNRES SNCL SNDA SMP M RESET SENSOR TDA878x CCD9 to CCD0 SDATA SCLK STROBE SAA8112HL DSP AND MICROCONTROLLER SAA8115HL USB INTERFACE V-DRIVER CLOCKON UCM UCCLK FS, FCDS, DCP, BCP, CLK1 C1 to C4, CR, RG A1 to A4, B1 to B4 FCE464 SMP TRC SUSPEND SUSPREADYNOT UCINT UCPOR DQ15 to DQ0 AD10 to AD0 RASB CASB WEB CLKEN DQM CSB 2000 Jan 27 EPPROM (optional) 14 APPLICATION INFORMATION Philips Semiconductors Digital camera USB interface EEPROM SDRAM (optional) 51 Preliminary specification SAA8115HL Fig.8 Typical USB camera application. Philips Semiconductors Preliminary specification Digital camera USB interface 15 PACKAGE OUTLINE LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SAA8115HL SOT486-1 c y X A 108 109 73 72 ZE e E HE A A2 A1 (A 3) Lp L detail X wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.50 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.40 1.10 1.40 1.10 7 0o o 22.15 22.15 21.85 21.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-03 00-01-19 2000 Jan 27 52 Philips Semiconductors Preliminary specification Digital camera USB interface 16 SOLDERING 16.1 Introduction to soldering surface mount packages SAA8115HL If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 16.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 16.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2000 Jan 27 53 Philips Semiconductors Preliminary specification Digital camera USB interface 16.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not SAA8115HL REFLOW(1) 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Jan 27 54 Philips Semiconductors Preliminary specification Digital camera USB interface 17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA8115HL This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Jan 27 55 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 69 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753505/03/pp56 Date of release: 2000 Jan 27 Document order number: 9397 750 06568 |
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